The present invention relates, in general, to a novel process for the fabrication of suspended high-aspect-ratio single crystal silicon microstructures. More particularly, the invention relates to two-, three- or more level, high-aspect-ratio, released, or suspended, single crystal silicon microstructures of complex geometries, wherein all levels are self-aligned and fabricated from a single silicon wafer, and to the isolation of or removal of selected suspended microstructures.
Interest in the fabrication of suspended microstructures has increased with the increased use of microelectromechanical systems (MEMS). Many MEMS implementations are fabricated by surface micromachining of deposited thin films, by bulk micromachining of (usually silicon) substrates, or by deep etching, as used in the Single Crystal Reactive Etching and Metallization (SCREAM) process, which is explained for example, in U.S. Pat. No. 5,198,390. As described in this patent, the SCREAM process produces a single level of suspended microstructures. Multiple level SCREAM microstructures must use multiple substrates bonded together, and most other prior techniques for fabricating multiple level structures require the assembly and alignment of numerous separately fabricated components. However, such assemblies are impractical for large arrays of micron-scale structures, and in particular for electron lenses and similar devices, where alignment is critical.
Another process for micromachining silicon substrates for fabricating microelectromechanical devices is exemplified by the process described in U.S. Pat. No. 5,501,893 to Laermer, et al. In this patent, an anisotropic plasma etching of silicon through a mask is used to provide laterally defined recesses in a substrate. The etching step is alternated with a polymerizing step which covers silicon surfaces exposed by the etching step to provide an etching stop, which prevents etching of those surfaces in a subsequent etch step. The alternating etching and protecting steps allow high anisotropy of the etched structure.
Although these processes have been successful, new technical demands have emerged for MEMS fabrication technology; in particular, the integration of MEMS with active electronics on the same chip, and the development of more complex microsystems. There is a need, therefore, for a process which will facilitate fabrication of single and multiple levels of released or suspended microstructures from a single substrate, and in particular will facilitate the fabrication of large arrays of these structures.
Briefly, the present invention is directed to improved fabrication processes for microelectromechanical structures, and to unique structures fabricated by the improved processes. In its simplest form, the invention is directed to a fabrication process which is based on both the method described, for example, in U.S. Pat. No. 5,501,893 to Laermer et al (hereafter Laermer et al) the disclosure of which is hereby incorporated herein by reference, and on the SCREAM process described, for example, in U.S. Pat. No. 5,198,390, the disclosure of which is hereby incorporated herein by reference. These processes are modified and extended and are used in such a way as to produce a combined vertical etch and release RIE process, which may be referred to herein as a xe2x80x9ccombination etchxe2x80x9d.
Fabrication of a single-level micromechanical structure using the process of the present invention includes a novel dry etching process to shape and release suspended single crystal silicon elements, in a single dry etch step. This new process combines vertical silicon reactive ion etching (Si-RIE) and release etches to eliminate the need to deposit and pattern silicon dioxide mask layers on the sides of suspended structures, as is required in the SCREAM process. It furthermore reduces the mechanical stresses in suspended structures caused by deposited silicon dioxide films.
Briefly, the combined process includes formation of a mask structure on the surface of a silicon substrate, for example, through conventional photolithography. Thereafter, the silicon is etched through the mask using an anisotropic vertical reactive ion etching (RIE) plasma etching process using a sequence of etch and passivation cycles as described by Laermer et al. A short quasi-isotropic Si-RIE is followed by a polymerization step which conformally coats the exposed surfaces with a passivation layer. Thereafter, a second anisotropic etching step is carried out which first removes the polymer coating from the horizontal surfaces of the substrate by sputter etching, but not from the vertical surfaces, and then etches the exposed silicon quasi-isotropically. These alternating steps are repeated to produce deep structures (or trenches) having vertical edges, with the profile of the structure being determined by the balance between the passivation and etching steps.
When the desired structure depth has been reached, the structure may be released from the substrate by adjusting the length of and balance between the passivation and etching steps. A long polymerization deposits a thicker passivation layer, followed by a longer Si-RIE step which undercuts the structure to release it. This process integrates the release of suspended structures with the vertical etch that defines them, and is much simpler than prior deep etching fabrication process sequences. It allows the fabrication of delicate structures by reducing mechanical stresses in them, due to the absence of stress-inducing sidewall passivation layers and by avoiding any wet process steps which could deform the suspended structures. The process is particularly suitable for integration with active sensing devices.
In accordance with this aspect of the invention, silicon suspended structures may be produced on a single crystal silicon (SCS) substrate, or wafer, which may contain prefabricated active devices, utilizing only four steps: (1) a photolithography step which defines the layout of the suspended structures and surrounding trenches in a resist layer on the substrate; (2) a first etching step in which the pattern is transferred to the field and inter-layer dielectrics are etched in an anisotropic RIE step; (3) a second etching step in which high aspect ratio SCS suspended structures are etched and released in a single combined etch, and (4) a final step in which the photoresist is removed. The sidewall silicon dioxide film deposition and etchback utilized in prior processes such as the SCREAM process is not necessary, and no further patterning steps for interconnecting the released structure to active devices on the wafer are required, in accordance with this process. On a blank silicon wafer without dielectric films step (2) can also be skipped, reducing the number of process steps for the fabrication of suspended single crystal silicon structures to 3.
The process of the present invention further comprises an extension of the SCREAM process to allow the fabrication of multiple level structures, including but not limited to, the selective removal of parts of levels. This extension of the process enables the fabrication of suspended elements of different heights, and reduces the process-imposed restriction of previous multiple level processes that all suspended levels must have the same layout. The extended process is applied to the fabrication of novel actuators, electron lenses and micromachines, and allows multiple levels of self-aligned, suspended structures with greater design flexibility.
In the basic SCREAM process, as described in U.S. Pat. No. 5,198,390, a thick silicon dioxide film (1.5-4 xcexcm) is placed on the surface of a substrate by thermal oxidation of the substrate or by CVD deposition. This film is patterned using a resist layer, photolithography, and CHF3-RIE. The silicon substrate is etched in a vertical RIE step, using the silicon dioxide and photoresist films as an etch mask. Typical etch depths range from 10 to 20 xcexcm. A subsequent thermal oxidation or CVD deposition covers the surface conformally with a thin (200-400 nm) silicon dioxide layer. A vertical RIE then removes this film from the horizontal surfaces, including the floor of trenches etched by the first vertical RIE; any silicon dioxide on the sidewalls of the SCS structure is not etched.
The top of the SCS structure is still covered with the remainder of the first, thicker silicon dioxide etch mask. A high-pressure (80-90 mTorr) isotropic SF6 RIE of silicon then undercuts the masked silicon structure, completing the fabrication of the first level of structures. In a final metallization step aluminium is deposited by sputtering, covering the released structures nearly conformally.
A multiple level structure can be fabricated using an extension of the SCREAM process, with the same four steps being repeated for each level of the structure: vertical Si-RIE, conformal silicon dioxide deposition, anistropic CHF3 RIE of silicon dioxide and quasi-isotropic RIE of silicon using SF6. After carrying out these steps for the first level of released silicon structures, the silicon substrate is again etched in a vertical RIE for a further 10-20 xcexcm, without the need for an additional lithographic step; instead, the whole upper-level masked silicon structure serves as a xe2x80x98shadow maskxe2x80x99 for this etch. The exposed silicon underneath the masked silicon structure is not etched due to the high degree of anisotropy of the vertical Si-RIE. The resulting lower-level silicon structure is self-aligned to the upper-level structure, but is slightly wider than the original width of the upper level, since the sidewall oxide deposition increased the width of the upper level structure. A thermal oxidation or CVD deposition again covers all surfaces conformally with silicon dioxide.
A vertical CHF3 RIE again is used to remove the oxide from the horizontal surfaces, with the top of the upper level of silicon structure still being covered by the remaining part of the first (thick) mask oxide. An isotropic SF6 RIE undercuts and releases the masked silicon structure to complete the fabrication of the second level of the microelectromechanical (MEM) structures. This sequence is repeated for each additional level.
In accordance with the present invention, fabrication of multilevel devices may be further simplified by using the combined etch process based on the SCREAM process and the etch process of Laermer et al. The combined etch is used to produce the first layer of a structure, and the SCREAM process is utilized for second and subsequent layers. This combination simplifies the fabrication of multilevel structures by omitting several of the silicon dioxide deposition and etchback steps that would be required if only the SCREAM process were to be used. The modified Laermer et al etch could be used for just one layer or for additional layers, but is not preferred for lower level structures due to the increased impact of its limitations; namely, the maximum linewidths which can be released and the decreasing effectiveness of the release etch in deep, narrow trenches.
After the completion of all levels of the suspended microstructure, a timed thermal oxidation step is used to isolate selected suspended SCS structures by consuming all the silicon in thin isolation segments and to increase the protection of the released structures during subsequent processing.
The structures are then covered with a thick photoresist film (typically 20-60 xcexcm) so a second lithography step may be used to open contact windows on the suspended structures. These windows are designed to be large enough ( greater than 20 xcexcm features) to be easily exposed in the thick resist and do not require critical alignment to the microelectromechanical beams (which typically are 0.6 to 4 xcexcm wide). Moreover, they do not have to be exposed through the full thickness of the resist but only down to the top of the upper level of the beams making up the isolation structures, when the contacts are to be made on the top surfaces. The resist forms an etch mask for a wet buffered oxide etch which may be used to open up the contact windows. This etch may also used to selectively remove the SiO2 films from parts of the suspended structure in which case The openings in the resist etch mask have to be large enough to enable the underlying structures to be exposed to the wet etch. After stripping the resist, contacts to the suspended silicon structures are formed by the evaporation of aluminum, followed by a sintering step.
The isolation and contact scheme for multiple-level self-aligned structures selectively contacts and isolates levels, individually as well as all of them simultaneously, while maintaining mechanical support of the suspended structures. Furthermore, the scheme provides a way to electrically connect to the suspended levels from the outside via contact pads through a combination of five elements, which provide (I) electrical isolation on all levels, but mechanical support from the substrate, (ii) electrical isolation within the suspended levels, (iii) isolation on one level while connecting the others, (iv) electrical connections between levels, and (v) electrical connection from an arbitrary level to the top of a contact pad. For practical reasons these pads are preferably at the wafer surface for all levels.
The multiple-level contact and isolation scheme of the invention makes use of the feature of the present process that the lower levels are wider than the upper levels, as described above, which widening is caused by the broadening of the structures in the sidewall oxide deposition step. As noted above, the upper level is etched by a vertical Si-RIE, which is followed by a thermal oxidation of the sidewalls. This oxidation step increases the width of the structures even though some of the silicon is consumed; the volume of the resulting silicon dioxide is 2.2 times larger, which leads to a net widening of the structures by an amount roughly equal to the film thickness. Alternatively, the sidewall film may be deposited by CVD, in which case the widening is twice the deposited film thickness. This widened structure now forms the mask for the vertical silicon RIE which defines the lower level structure. This lower level structure is thus wider than the upper level by about the sidewall film thickness. Both levels are again thermally oxidized and then the lower level is released as well. This may be followed by a long oxidation step, designed to consume all the silicon in the thinnest segments of the released beams to produce silicon dioxide isolating segments in the beams.
The strength of this isolation scheme is the simplicity of the process sequence, for only one lithography step and one metal deposition is required, independent of the number of levels. Thermal silicon dioxide bridges provide high quality insulation between suspended levels and the substrate with low leakage currents and high breakdown voltages.
The present invention, in another aspect, comprises new types of actuators using multiple levels of electrodes which preferably are fabricated using the improved process of the invention. These actuators show an increased range of motion compared to conventional single-level electrostatic comb actuators and generate higher forces. They include designs which operate bi-directionally and allow multistable configurations. As these new actuator designs generate a higher force per substrate area used, they are of particular interest for the integration of dense arrays of actuators. In order to effectively use the advantages of the multiple-level designs, the gaps between the electrodes need to be kept small, and the electrodes accurately aligned.
In still another aspect, the present invention comprises a new type of clamping device, which allows the accurate positioning and clamping of micro- to mini-scale elements, such as optical fibers, by exploiting the self-aligned nature of the multiple levels.